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## Low Computational Complexity and High Computational Speed in Leading DCD ERLS Algorithm | ||

Journal of Electrical and Computer Engineering Innovations (JECEI) | ||

مقاله 4، دوره 7، شماره 1، بهار 2019، صفحه 19-26
اصل مقاله (1.16 MB)
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نوع مقاله: Original Research Paper | ||

شناسه دیجیتال (DOI): 10.22061/jecei.2019.5666.243 | ||

نویسندگان | ||

F. Abdi؛ P. Amiri ^{} ؛ M.H. Refan
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^{}SRTTU | ||

تاریخ دریافت: 23 تیر 1398، تاریخ بازنگری: 16 شهریور 1398، تاریخ پذیرش: 24 شهریور 1398 | ||

چکیده | ||

Adaptive algorithm adjusts the system coefficients based on the measured data. This paper presents a dichotomous coordinate descent method to reduce the computational complexity and to improve the tracking ability based on the variable forgetting factor. Vedic mathematics is used to implement the multiplier and the divider operations in the VFF equations. The proposed method decreases the area and increases the computation speed. The linear exponentially weighted recursive least squares as the main algorithm is implemented in many applications such as the adaptive controller, the system identification, active noise cancellation techniques, and etc. The DCD method calculates the inverse matrix in the ERLS algorithm and decreases the resources used in the field-programmable gate array, also the designer can use the cheaper FPGA board to implement the adaptive algorithm because the method doesn't need lots of resources. The proposed method leads to implementing complex algorithms with simple structures and high technology. The proposed method is implemented with ISE software on the Spartan 6 Xilinx board. The proposed algorithm calculates the multiplication result with less than 15ns time and reduces the used FPGA resources to lower than 20% as compared with the classic RLS. | ||

کلیدواژهها | ||

Exponentially weighted Recursive least squares (ERLS)؛ Dichotomous coordinate descent (DCD)؛ Variable forgetting factor (VFF)؛ Field-programmable gate array (FPGA) | ||

مراجع | ||

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